1. Technical Field
Various embodiments generally relate to a semiconductor circuit, and more particularly, to a semiconductor apparatus capable of self-tuning a timing margin.
2. Related Art
A semiconductor apparatus should receive an external command based on an external clock signal. The semiconductor apparatus may perform an operation according to the external command in conformity with a predetermined latency.
The latency may define that the operation according to the external command should be performed at which clock pulse from a clock pulse with which the external command is synchronized based on the external clock signal.
The semiconductor apparatus generates an internal clock signal for synchronizing data output or an on-die termination operation with the rising edge of the external clock, that is, a delay-locked loop clock signal, by using a delay-locked loop which models an internal signal path.
Accordingly, the semiconductor apparatus should synchronize an internal signal which determines a data output timing or an on-die termination timing, with the delay-locked loop clock signal.
However, as a variation occurs in PVT (process, voltage and temperature), the phase difference between the external command and the delay-locked loop clock signal may be distorted. This distortion may be beyond a predetermined margin, and accordingly, an operation error may be caused.